The inventive concepts described herein generally relate to semiconductor memory devices which include transistors containing a nitride liner between a gate and source/drain regions.
Generally, the transistors of such devices, such as DRAM (dynamic random access memory) devices, disadvantageously exhibit a wide threshold voltage distribution of such devices.
The inventive concepts described herein more particularly relate to methods for equalizing trap charges in semiconductor memory device transistors, thereby reducing the threshold voltage distribution of the transistors.
According to an aspect of the inventive concepts, a method is provided for reducing a threshold voltage distribution in transistors of a semiconductor memory device, where each transistor includes a nitride liner. The method includes injecting electrons into a charge trap inside and outside the nitride liner of the transistors, and partially removing the electrons injected into the charge trap inside and outside the nitride liner to equalize trapped charges in the transistors.
According to another aspect of the inventive concepts, a method is provided for reducing the distribution of threshold voltages of a plurality of transistors of a semiconductor memory device including a shallow trench isolation (STI) structure comprising a nitride liner. The method includes selecting transistors that are positioned in a region where acceptor segregation has occurred from among the plurality of transistors, and injecting electrons to a trap inside and outside the nitride liner of the selected transistors. A quantity of injected electrons is increased with an increased occurrence of the acceptor segregation among at least one of the selected transistors.